A technique used to support faster sequential access to DRAM by allowing any number of accesses to the currently open row to be made after supplying the row address just once.
The RAS signal is kept active, and with each falling edge of the CAS\ signal a new column address can be supplied and the corresponding bits can be accessed. This is faster than a full RAS-CAS cycle because only the shorter Column Access Time needs to be obeyed.
Note that strictly speaking such a DRAM is not a true random access memory since accesses to the open row are faster than to other locations.
EDO RAM is replacing Page Mode DRAM in many new microcomputers.
[Is "Fast Page Mode" the same as "Page Mode"?]